1. Field of the Invention
The present invention generally relates to a method and apparatus for circuit design (e.g., complementary metal oxide semiconductor (CMOS) circuit design) and to wiring integrated circuits (ICs), and more particularly to a method and apparatus for wiring ICs with multiple power buses based on performance.
2. Description of the Related Art
Conventional systems utilizing low power logic applications are growing rapidly as mobile communications (e.g., personal communications services, personal communication/data assistants, etc.) and pervasive computing become entrenched in modern society.
However, a dilemma faced by the integrated circuit (IC) designer is how to provide the computing performance to enable advanced features, such as voice recognition etc., while operating with a limited power supply (e.g., batteries). One solution is to provide high voltage power busing only for those circuits most critical for performance, and lower voltage power busing for less critical circuits.
However, this approach is problematic in that there is no method of determining how such power supplies should be optimally partitioned.
Further, there is a problem of crossing a low voltage logic path over to a path powered by higher voltages. Specifically, the problem is the inability of the lower output voltage to shutoff the transistor (e.g., PFET) load devices.